1. Field of the Invention
This invention relates to a method of producing semiconductor devices and, in particular, to a method of producing semiconductor devices of a MONOS (metal oxide nitride oxide semiconductor) type.
2. Description of the Related Art
As a semiconductor nonvolatile-storage device capable of realizing a reduction in program voltage, a MONOS-type semiconductor nonvolatile storage device has been used, which includes: a semiconductor substrate; a gate insulating layer formed in a channel area on the semiconductor substrate and composed of a lower silicon oxide layer (a tunnel oxide layer), a silicon nitride layer, and an upper silicon oxide layer (a top oxide layer), which are arranged in that order from the side of the semiconductor substrate; and a gate electrode provided on the gate insulating layer.
This semiconductor storage device has usually been produced by the following method, which is illustrated in FIGS. 8 through 12:
First, the surface of a silicon semiconductor substrate 1, which has been separated into device regions by a selectively formed oxide layer 2, is subjected to thermal oxidation to form a lower silicon oxide layer 3 which is as thin as approximately 20.ANG.. Then, a silicon nitride layer 4 having a thickness of 20.ANG. to 150.ANG. is formed on the lower silicon oxide layer 3 by CVD (chemical vapor deposition). Further, a top oxide layer 5 having a thickness of approximately 40.ANG. is formed on the silicon nitride layer 4 by thermal oxidation or CVD.
When forming the top oxide layer 5 of the silicon nitride layer 4 by thermal oxidation, steam oxidation is performed at a temperature of 900.degree. to 950.degree. C. In that process, the silicon nitride layer 4 becomes thinner, being consumed to a thickness corresponding to 1/1.6 of the grown oxide layer. In this way, a gate insulating layer 7 having a triplex structure is formed.
Next, a polycrystalline silicon layer 6 is formed by CVD on this gate insulating layer, as shown in FIG. 8.
Subsequently, a resist 8 is applied to the polycrystalline silicon layer 6 and is exposed and developed to effect patterning. After that, the polycrystalline silicon layer 6 is selectively removed to form a gate electrode 9 consisting of a part of the polycrystalline silicon layer 6 on the substrate 1 through the intermediation of the gate insulating layer 7, as shown in FIG. 9.
Then, the gate insulating layer 7 is selectively removed so as to leave only that portion thereof which is under the gate electrode 9, thereby partly exposing the semiconductor substrate 1, as shown in FIG. 10.
Next, the resist layer 8 is removed and, as shown in FIG. 11, a silicon oxide layer 10 is formed by oxidation on the gate electrode 9 and on the exposed portion of the semiconductor substrate 1. This silicon oxide layer 10 is utilized as an inter-layer insulating layer surrounding the gate electrode 9 and as the address gate of the semiconductor substrate 1 or the gate insulating layer of a peripheral circuit.
Further processes, such as the formation of an address electrode, are performed. In this way, a semiconductor nonvolatile storage device is completed.
In the conventional production method described above, etching is performed when the procedure advances from the condition shown in FIG. 9 to that shown in FIG. 10. That is, when selectively removing the gate insulating layer 7 in such a way as to leave only that portion thereof which is under the gate electrode 9, the etching is performed until the semiconductor substrate 1 is exposed.
However, terminal control in the etching of the gate insulating layer 7 to expose the semiconductor substrate 1 is very difficult, normally resulting in overetching.
Thus, the exposed surface of the semiconductor substrate 1 is rather rough, which leads to impaired induction, etc. Further, the above etching leads to a phenomenon generally called "overhang" in which the gate insulating layer 7 is partially cut, as indicated at 11 in FIG. 12.
These problems cause a deterioration in gate withstand voltage and a dispersion in initial memory characteristics, adversely affecting the memory properties. Further, the problems lead to a deterioration in the write/erase and data retention properties of the storage device, generation of an interfacial level, etc., thereby decreasing the reliability of the semiconductor storage device.